Redfire75369’s Twitter Archive—№ 3,849

@ieee_iedm is happening in a week! I've looked through the programme and listed some (a lot) interesting sessions below. Do note that this is only my personal opinion and I've generally skipped stuff I don't understand. Look through it yourself for a better recommendation. (1/x)
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Short Course 1: Intel: Future of High-Performance Computing: Software, System and Transistor Samsung: Energy-Efficient CMOS scaling for 1nm and beyond (2/x)
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Short Course 1 (cont.): TSMC: Novel Logic devices for Energy Efficient Computing UCLA: Heterogenous integration and Chiplet packaging imec: Process Architectures Changes To Improve Power Delivery UC Berkeley: Optical Interconnects (3/x)
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Short Course 2: AMD: Memory solutions for HPC & AI: An Overview TSMC: High-speed SRAMs for Future HPC and AI Samsung: Next-Generation DRAM for HPC and AI Princeton: Future Prospect of In- and Near-Memory Computing U of Georgia: High-Speed Emerging Memories for AI and HPC (4/x)
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Short Course 2 (cont.): imec: Innovative 3D Technologies for Memory-Compute Integration Yes, that's all of both the short courses. (5/x)
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Session 1: Intel: Celebrating 75 years of transistor innovation by looking ahead to the next set of great innovation opportunities CEA-Leti: Enabling full fault tolerant quantum computing with silicon based VLSI technologies (6/x)
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Session 2: U Tennessee: Application-Hardware Co-Design: System-Level Optimization of Neuromorphic Computers with Neuromorphic Devices (7/x)
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Session 3: A*STAR: Advanced System in Package Enabled by Wafer Level Heterogeneous Integration of Chiplets TSMC: Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R) ASE: Advanced Packaging Technology Platforms for Chiplets and Heterogeneous Integration (8/x)
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Session 3 (cont.): Intel: Advanced Substrate Packaging Technologies for Enabling Heterogeneous Integration (HI) Applications Unimicron: Hybrid Substrates for Chiplet Design and Heterogeneous Integration Packaging (9/x)
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Session 3 (cont.): Samsung: Advanced Package FAB Solutions (APFS) for Chiplet Integration (10/x)
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Session 5: Seoul National U + SK Hynix: Retention Improvement in Vertical NAND Flash Memory Using 1-bit Soft Erase Scheme and its Effects on Neural Networks (11/x)
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Session 6: Intel: Hafnia-Based FeRAM: A Path Toward Ultra-High Density for Next-Generation High-Speed Embedded Memory (12/x)
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Session 7: TSMC + National Cheng Kung U + National Taiwan U: pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping (13/x)
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Session 7 (cont.): Intel: Gate length scaling beyond Si: Mono-layer 2D Channel FETs Robust to Short Channel Effects U of Hong Kong: Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors (14/x)
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Session 8: UC Berkeley + Indian Institute of Technology: Compact Modeling of Emerging IC Devices for Technology-Design Co-development Intel: Mitigating Impact of Defects On Performance with Classical Device Engineering of Scaled Si/SiGe Qubit Arrays (15/x)
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Session 9: GE Research + Rensselaer Polytechnic Institute: Scalable Ultrahigh Voltage SiC Superjunction Device Technologies for Power Electronics Applications (16/x)
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Session 10: IBM Research: Double spin-torque magnetic tunnel junction devices for last-level cache applications Samsung: World-most energy-efficient MRAM technology for non-volatile RAM applications (17/x)
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Session 12: IBM Research + Samsung: Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling (18/x)
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Session 12 (cont.): National U of Singapore + Soitec: First Demonstration of BEOL-Compatible 3D Fin-Gate Oxide Semiconductor Fe-FETs Applied Materials: MOL Local Interconnect Innovation: Materials, Process & Systems Co-optimization for 3nm Node and Beyond (19/x)
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Session 14: IBM Research + U of Basel: Spin Qubits in Silicon FinFET Devices New York U: Towards Topological Superconducting Qubits Tokyo Institute of Technology: Potential of diamond solid-state quantum sensors (20/x)
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Session 15: Global TCAD + Huawei + Hisilicon: Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node (21/x)
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Session 15 (cont.): National Taiwan U: Energy- and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors (22/x)
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Session 17: Columbia U: Single-molecule field-effect transistors: carbon nanotube devices for temporally encoded biosensing CNRS - IRISA: DNA storage: synthesis and sequencing semiconductor technologies (23/x)
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Session 17 (cont.): U of Washington: System Design Considerations for Automated Digital Data Storage in DNA (24/x)
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Session 18: Tsinghua U + Chinese Academy of Sciences: A Hybrid Computing-In-Memory Architecture by Monolithic 3D Integration of BEOL CNT/IGZO-based CFET Logic and Analog RRAM (25/x)
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Session 18 (cont.): Powerchip + Semiconductor Energy Laboratory + National Taiwan U: A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO 2/Al 2O 3/ZrO 2 for Ultra-Low Power Edge AI Application (26/x)
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Session 18 (cont.): SK Hynix: Extremely high performance, high density 20nm self-selcting cross-point memory for Compute Express Link (27/x)
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Session 19: imec + KULeuven: Colloidal quantum dot image sensors: a new vision for infrared (28/x)
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Session 20: KAIST + Hanyang U: Heterogeneous 3D Sequential CFET with Ge (110) Nanosheet p-FET on Si (100) bulk n-FET by Direct Wafer Bonding (29/x)
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Session 20 (cont.): National Cheng Kung U + Taiwan Semiconductor Research Institute + National Yang Ming Chiao Tung U First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes (30/x)
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Session 20 (cont.) National Cheng Kung U + National Yang Ming Chiao Tung U + National AIST + Sun Yat-Sen U: Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size (31/x)
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Session 21: U of Zurich + ETH Zurich: Energy-efficient activity-driven computing architectures for edge intelligence Purdue U + Ludwig Computing: Life is probabilistic - Why should all our computers be deterministic? Computing with p-bits: Ising Solvers and Beyond (32/x)
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Session 21 (cont.): Rain Neuromorphics: Scalable In-Memory Computing Architectures for Sparse Matrix Multiplication Mythic: Analog Compute-in-Memory For AI Edge Inference [Slight Oof] (33/x)
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Session 22: CEA-LETI + CNRS Neel Institute + CEA-Irig + U Grenoble Alps: Methodology for an efficient characterization flow of industrial grade Si-based qubit devices (34/x)
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Session 22 (cont.): Intel + KAIST: Scalable In-Memory Clustered Annealer with Temporal Noise of FinFET for the Travelling Salesman Problem Fudan U + George Mason U: Steep-Slope Negative Quantum Capacitance Field-Effect Transistor (35/x)
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Session 23: imec: Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures imec: Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells (36/x)
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Session 23 (cont.): Grenoble INP - Phelma: Insights into Scaled Logic Devices Connected from Both Wafer Sides imec: Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network (37/x)
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Session 23 (cont.): Arizona State U + U of Wisconsin-Madison: AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-memory Acceleration (38/x)
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Session 24: NIST + CEA-Leti + U Grenoble Alps: High-Resolution DNA Binding Kinetics Measurements with Double Gate FD-SOI Transistors (39/x)
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Session 25 (Panel): 75 years of transistor technology – (no) time for retirement? Panelists: imec, LAM, TEL, SK Hynix (former CEO), Intel, Micron, NIST, IBM (40/x)
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Session 27: TSMC: Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond STMicro + Samsung: 18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs (41/x)
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Session 27 (cont.): Intel: Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process TSMC: A 3nm CMOS FinFlex TM Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications [!!!] (42/x)
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Session 33: IBM Research: Gradient descent-based programming of analog in-memory computing cores Samsung: MRAM In-memory computing macro for AI computing Macronix: An Analog In-Memory-Search Solution based on 3D-NAND Flash Memory for Brain-Inspired Computing (43/x)
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Session 33 (cont.): IBM Research + TEL + TSMC: Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization (44/x)
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Session 34: Chinese Academy of Sciences: Record 7(N)+7(P) Multiple V Ts Demonstration on GAA Si Nanosheet n/pFETs using WFM-Less Direct Interfacial La/Al-Dipole Technique IBM + Samsung: Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology (45/x)
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Session 35: Transphorm: 1200V GaN Switches on Sapphire: A low-cost, high-performance platform for EV and industrial applications (46/x)
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Session 36: imec: First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories Intel: Low-voltage and high-speed switching of a magnetoelectric element for energy efficient compute (47/x)
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Session 37: California Institute of Technology: Coherent Silicon Photonics for Imaging and Ranging STMicro + CEA-Leti + U Grenoble Alps: 3-Tier BSI CIS with 3D Sequential & Hybrid Bonding Enabling a 1.4um pitch,106dB HDR Flicker Free Pixel (48/x)
Permalink On twitter.com ❤️ 4 Favorites 2022 Nov 27 Mood +1 🙂

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Session 37 (cont.): Samsung: 3-Layer Stacked Voltage-Domain Global Shutter CMOS Image Sensor with 1.8μm-Pixel-Pitch (49/x)
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A final reminder that these are just my own opinions and you should look at the programme yourself. If there's a few mistakes, I'm sorry because this was probably way too long a thread and I couldn't check the whole thing thoroughly. ieee-iedm.org/program-overview
Permalink On twitter.com ♻️ 1 Retweets ❤️ 5 Favorites 2022 Nov 27 Mood -3 🙁