Redfire75369’s Twitter Archive—№ 3,600

@chiakokhua @TheKanter @ChipsandCheese9 @lamchester Personally, I was thinking it was just going to hold some cache that could be shared across all the tiles, along the interconnects of course. That part can mostly be inferred from the size of the SoC tile. I wasn't expecting it to be fully passive, but isn't that far of a jump.