Redfire75369’s avatarRedfire75369’s Twitter Archive—№ 3,052

  1. …in reply to @Locuza_
    @Locuza_ @GPUsAreMagic Both OneDNN and Intel's Optimisation Guide state that all Xe architectures have 128K SLM. I wonder if, for example on Xe-HPC, there's 512K that can be either L1D$ or SLM, which is programmable, but the SLM has a limit of 128K.
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    1. …in reply to @Redfire75369
      @Locuza_ @GPUsAreMagic AnandTech: > Information about this cache is limited, but Intel has confirmed that it’s a 64KB per subslice cache, and that it can be dynamically reconfigured between L1 and texture caching as necessary. anandtech.com/show/15973/the-intel-xelp-gpu-architecture-deep-dive-building-up-from-the-bottom/5
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      1. …in reply to @Redfire75369
        @Locuza_ @GPUsAreMagic Optimisation Guide: intel.com/content/www/us/en/develop/documentation/oneapi-gpu-optimization-guide/top/xe-arch.html OneDNN: github.com/oneapi-src/oneDNN/blob/62a05c34fd0bf46ff3a0f0cf4a4a4e4f0d2cf0db/src/gpu/compute/device_info.cpp#L119-L122
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