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We now have pictures of the Ponte Vecchio package without the tiles on it, similar to Sapphire Rapids-HBM. 1. Ponte Vecchio Package 2. Sapphire Rapids-HBM Package nytimes.com/2022/04/08/technology/intel-chip-shortage.html
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By my crude estimation, there should be ~5400 pins for MDF between the base tiles and ~2850 pins for MDF between the base and Xe Link tile. That means about 105-110W of power is used just for D2D communication, excluding HBM.
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MDF (Base-Base): 5.4 Gb/s/pin MDF (Base-Xe Link): 2.7 Gb/s/pin FDI (Base-Compute): 2.6 TB/s FDI (Base-RAMBO): 1.3 TB/s MDF: 0.5 pJ/b FDI: 0.2 pJ/b
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