Redfire75369’s avatarRedfire75369’s Twitter Archive—№ 2,863

      1. Interesting Section about Xe on the Developer Guide for oneAPI: This talks about Xe-LP, Xe-HPG and Xe-HPC. This mostly talks about architectural details, although its not super low-level either. 🧵(1/x) intel.com/content/www/us/en/develop/documentation/oneapi-gpu-optimization-guide/top/xe-arch.html
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      It talks about what a dual subslice is, seems to be due to the presence of dual EUs. Drivers imply a dual subslice can have two subslices though, which is still weird. (2/5)
      oh my god twitter doesn’t include alt text from images in their API
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    It has a table showing the changes in terminology from Pre-Gen12.7 to Post-Gen12.7. It also confirms that Xe-HPG is Gen12.71 and not Gen12.5 (That's ATS). They don't mention L3 becoming L2 though. (3/5)
    oh my god twitter doesn’t include alt text from images in their API
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      Importantly, it also shows a summary of various Xe GPU configurations. It confirms 16 MiB LLC (L2) for Xe-HPG, even though that isn't public yet. SLM$ is 128 KiB regardless of the architecture. (4/5)
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        Xe-HPG does not support FP16 DP4AS, seemingly, which is weird. It also shows that Xe-HPC is 2x performance/XVE/clock in everything because of the fused dual EU, though that's obvious. (5/5)
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