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AMD Sabrina Board: Chausie Package: FP6 (same as CZN) UART Controllers: 4 (Up from 2 in RNR/CZN) [Zen+ APUs had 4] No CPPC2 μarch: Zen/+/2 PCIe: 1 GPP (2 on RNR/CZN) [Not split into 3] SATA: None Similar to Dali coelacanth-dream.com/posts/2022/01/14/amd-sabrina-soc-more-patch/
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I don't actually know what I'm talking about for PCIe GPP, so forgive me if I messed it up.
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