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Bringing Geek Back: Q&A with Intel CEO Pat Gelsinger This thread is just interesting stuff (to me). anandtech.com/show/17042/bringing-geek-back-qa-with-intel-ceo-pat-gelsinger
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IDM + IFS Advantage: In a quick example of both, for IDM, my foundry customers get to leverage all of the R&D and IP that I'm creating through my internal design.
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IFS (1/2): We're engaging with a third-party IP ecosystem more aggressively, and with the EDA tool vendors more aggressively.
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IFS (2/2): For instance, our engagement with Qualcomm - they're driving us to do a more aggressive optimization for power and performance, more than our more performance-centric product lines would be.
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Aurora Write-Offs (1/2): Some of those changes lead to the write-off that we're announcing right now. The way the contract is structured, part of it is that the moment that we deliver a certain thing, we will incur some of these write-offs simply from the accounting rules (...)
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Aurora Write-Offs (2/2): (...) associated with it. As we start delivering it, some of those will likely get reversed next year as we start ramping up the yields of the products. So some of it just ends up being how we account for and how the contracts were structured.
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IBM Collaboration (1/3): But basically, we're partnering with IBM - think of them as another components research partner with us, in advanced semiconductor research, as well as in advanced packaging research. We're partnering with IBM in those areas.
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IBM Collaboration (2/3): Also, IBM is looking for a partner as well on their manufacturing initiatives, and what they require for their products and product lines. We're aligning together on many of the proposals that you've seen, (...)
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IBM Collaboration (3/3): such as the Ramp-C proposal that we were just granted. Phase one of that involves IBM partnering with us in those areas, so it’s a fairly broad relationship. You'll be hearing more from us before the year-end I expect.
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Capital Expenditure (1/4): For instance, right now, I lust for more fab capacity. Intel has under-invested [in fab capacity] for a number of years. Intel always used to have a spare shell (basically a fab building without any manufacturing equipment).
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Capital Expenditure (2/4): This is [going to be] one of the principles of our Smart Capital – we always have to have spare shells. If you take an Intel 20A Fab, it’s going to cost around $10 billion - but you can invest about $2B in the first two years [on the shell].
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Capital Expenditure (3/4): So part of our initiative is to build shells - get that greenfield capacity in place such that we can build shells and have more flexibility. [It also gives us] choice in the timing of the actual capital build.
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Capital Expenditure (4/4): Third, we've said we're going to capitalize some of these expanded capabilities based on government investments as well as customer investments.
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IFS IP (1/7): We are going to make x86 cores available, as standard IP blocks, on Intel Foundry Services. So if you use an Intel process, we will have versions of the x86 cores available. I do say cores, because it's going to be based on the cores that we're building – (...)
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IFS IP (2/7): (...) the E-cores and P-cores for standard product lines, we will be making them available.
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IFS IP (3/7): We're working on the roadmap of cores right now. That’s to say which ones become available, [whether that’s] big cores, little cores, which ones come first, and the timing for those - there's also a fair amount of work to enable the x86 cores with the ecosystem.
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IFS IP (4/7): As you all know very well, the Arm ecosystem has developed interface standards, and other ways to composite the entire design fabric. So right now we're working on exactly that.
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IFS IP (5/7): A fair amount of the IP world is using Arm constructs versus x86 constructs right now - these are interrupt models, things like memory ordering models, and there's a variety of those differences that we're haggling through right now.
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IFS IP (6/7): Then the lag side - there's got to be minimal lag. My IP teams internally, they act like a Synopsis IP team, because they're delivering for instance, an E-core or P-core to the Xeon design team, or to the Meteor Lake design team, [or others].
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IFS IP (7/7): So as those cores become available, we're going to be making those available to our internal teams and our external teams somewhat coincidently going forward so there's not a lag.
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