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    1. I'm currently reading something, and it states that Intel 4 uses 12 EUV layers. I'm really not sure how accurate that is. Does anyone have any ideas? It is just about equal to N5 at 11-13 EUV layers, so it might be feasible.
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  1. …in reply to @Redfire75369
    According to this one though, it's 13 layers: semiwiki.com/forum/index.php?threads/tsmc-to-reduce-euv-layers-for-3nm-as-part-of-cip.14536/post-48062
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